The Hardware Compilation Group at at the
Programming Research Group (PRG) within the
Oxford University Computing Laboratory (OUCL)
is led by Ian Page. If is
investigating the compilation of high-level occam-like programming languages
such as Handel (based on
CSP) directly into netlists of basic
digital hardware components suitable for loading onto a
Field Programmable Gate Array (FPGA). A
10-page summary of the state of research in the Hardware
Compilation Group is available.
An electronic mailing list exists for distributing information
concerning the group's activities, including details of seminars, and
also other messages of interest to the group. To join, please send
email including your contact details to
hwcomp-request@comlab.ox.ac.uk. Post messages intended
for distribution on the list to hwcomp@comlab.ox.ac.uk. At
the PRG, this list is gatewayed to the
local newsgroup
prg.hwcomp which includes announcements of relevant
seminars, particularly those organized by Mike Spivey.
A more general comp.arch.fpga newsgroup on
FPGAs was approved in July
1994 and is
archived.
A number of
hardware compilation papers are available on-line.
The seminal paper of the OUCL
Hardware Compilation Group was:
Compiling Occam into Field-Programmable Gate Arrays,
Ian Page and
Wayne Luk.
In W. Moore and W. Luk, FPGAs,
Oxford
Workshop on Field Programmable Logic and Applications, Abingdon EE&CS
Books, 15 Harcourt Way, Abingdon OX14 1NV, UK, pp 271-283, 1991.
Information on
Provably Correct Systems as applied to hardware
compilation, including a list of publications, is available.
-
FPL'94, 4th International Workshop on
Field Programmable Logic and Applications,
Prague, Czech Republic,
7-9 September 1994.
-
FPGA'95, ACM/SIGDA International Symposium on
Field-Programmable Gate Arrays,
Chaminade at Santa Cruz, California, USA, 12-14 February 1995.
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ISSS'95, 8th International Symposium on System Synthesis
Cannes, Cote d'Azur, France, 13-15 September 1995.
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ICCD'95, International Conference on Computer Design,
Austin, Texas, USA, 2-4 October 1995.
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On-line posters on the
work of the hardware compilation group.
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Information on the
HARP1
board, developed at the OUCL by Adrian
Lawrence, including a
transputer and FPGA hardware, useful for
experimenting with hardware/software co-design.
See colour photograph.
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Papers on
Ruby, a relational programming language suited for the design of
synchronous hardware, by
Geraint Jones and Mary Sheeran.
-
Information on
Geraint Jones'
Computer Architecture course.
-
Provably Correct Hardware/Software Co-design
EPSRC project.
-
APR (auto-place and route)
tool for PCs from Pilkington Micro-electronics Ltd. for their FPGA architecture.
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Links to
FPGA information and
VLSI information including meetings, tools, organizations,
projects, etc.
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Microprocessor instruction set cards.
-
Pentium FPU errors.
See also
comp.sys.intel newsgroup.
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Designing Correct Circuits proceedings, 1992.
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Theorem Provers in Circuit Design proceedings, 1992.
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Computer Hardware Description Languages and
their Applications proceedings, 1993.
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Formal Design Methods for CAD proceedings, 1994.
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Configurable array logic project at
University of St. Andrews, Scotland.
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NLC: C++ to Xilinx FPGA netlist compiler (Beta quality)
from Christian Iseli
Christian.Iseli@di.epfl.ch,
LSL-DI-EPFL, Lausanne, Switzerland..
-
Xilinx, USA.
Leading Field-Programmable Gate Array (FPGA) manufacturer.
-
Configurable Computing by
John Villasenor and William H. Mangione-Smith,
Scientific American, June 1997.
-
Virtual Computer Corporation including
Field Programmable Gate Arrays (FPGAs) information and
H.O.T. Works (Hardware Object Technology), a
hardware/software co-design system.
-
FPGA research, University of Toronto, Canada.
Last updated by
Jonathan Bowen,
21 September 1998.
Comments,
information suitable for inclusion and
pointers to relevant on-line papers are welcome.
Part of the OUCL
Hardware Compilation Group
information.
Hardware Compilation Resources